The complementary metal oxide semiconductor (CMOS) fabrication technology has become a common fabrication method of application specific integrated circuits (ASIC). Today, electrically erasable programmable read only memories (EEPROM) have been widely used in electronic products because of their non-volatile functions of electrically writing and erasing data.
Nonvolatile memory cells are programmable. Electric charges are stored to change the gate voltages of memory cell transistors, or electric charges are not stored to keep the original gate voltages of memory cell transistors. The erase operation removes all electric charges stored in nonvolatile memory cells to let all nonvolatile memory cells restore to the original gate voltages of memory cell transistors. Therefore, in the structure of a conventional nonvolatile memory cell, an extra conducting layer is added to store electric charges in addition to the gate layer of the transistor, hence forming a double-layer structure. As compared to the common CMOS fabrication process, there are more steps of film deposition, etch, and photolithography, hence increasing the cost, complicating the process, lowering the yield and lengthening the fabrication time.
A single-gate EEPROM structure has thus been proposed. This structure, however, has the problems of low reliability, interference from non-selected memory cells during the program step, and over erase. FIG. 1 shows a conventional EEPROM memory cell structure. N-type doped regions as a source 12 and a drain 14 are formed in a p-type semiconductor substrate 10. A channel is formed between the source 12 and the drain 14. A silicon dioxide 16, a catch layer (e.g., silicon nitride) 18, and an oxide 20 are formed in order on the surface of the substrate. A control gate 22 is disposed on the surface of the oxide 20. When a program/erase/write operation is performed to this memory cell, it is necessary to provide a large enough voltage for the drain and the source to finish the above action through a channel formed by this high voltage difference. Therefore, for the conventional single-gate EEPROM, the whole operation current can't be reduced easily. The operation current will be slightly high. Moreover, because the memory cell array becomes denser and denser, the channel length shortens accordingly, hence causing mutual interference between memory cells. Furthermore, a complicated peripheral circuit design is required for a higher operation current. Therefore, the above high-voltage operation method will increase the complexity of the peripheral circuit.
Besides, in the erase method of the conventional EEPROM, stored electric charges will move from the floating gate to the transistor to be removed due to the Fowler-Nordheim tunneling (F-N tunneling) effect. Because the structure of a single-gate EEPROM memory cell is a sandwich structure of transistor substrate-floating gate-capacitor substrate, stored electric charges can be released to either direction according to the direction of the applied electric field, hence more deteriorating the problem of over erase of the single-gate EEPROM.
Accordingly, the present invention aims to propose a modified structure of a nonvolatile memory cell and a method of operating the same to effectively solve the above problems in the prior art and also shrinking the memory cell.